The Anti-Tamper Digital Clocks Diaries

The Anti-Tamper Digital Clocks Diaries

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seventeen. The equipment for detecting clock tampering as defined in claim fifteen, wherein the Assess circuit is brought on by a clock edge at an stop in the clock Appraise time period.

Resettable hold off line segments involving a resettable delay line phase 210-one linked to a minimal delay time as well as a resettable hold off line phase 210-N associated with a most delay time are Every connected to discretely increasing delay occasions. An Consider circuit 240 is brought on by a clock CLK and takes advantage of the plurality of delayed monotone signals to detect a voltage fault.

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10. The equipment for detecting clock tampering as described in claim 8, whereby the means for triggering the suggests for assessing takes advantage of a clock edge at an stop of your clock evaluate period of time to result in the implies for assessing.

2. The strategy for detecting clock tampering as outlined in declare one, further comprising: resetting the resettable delay line segments in the course of a reset period of time, wherein the reset time frame is just before the clock Appraise time period.

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With even more reference to FIG. 7, One more element of the creation may perhaps reside within an apparatus for detecting clock tampering, comprising: a primary circuit 750A, a first plurality of resettable delay line segments 710, a 2nd circuit 750B, a next plurality of resettable delay line segments 720, and an evaluate circuit 240. The very first circuit delivers a first monotone sign during a first clock Examine time period connected with a clock. The main plurality of resettable delay line segments each hold off the initial monotone check here sign to produce a respective first plurality of delayed monotone signals. Resettable delay line segments between a resettable hold off line segment connected with a minimum delay time along with a resettable hold off line segment affiliated with a utmost delay time are Every associated with discretely expanding hold off occasions. The second circuit presents a 2nd monotone sign during a 2nd clock Assess period of time associated with the clock.

a plurality of resettable hold off line segments that hold off the monotone sign to deliver a respective plurality of delayed monotone alerts Each and every owning either a one particular or a zero logic worth, wherein resettable delay line segments amongst a resettable hold off line section linked to a minimum amount hold off time as well as a resettable hold off line segment associated with a maximum hold off time are Every connected with discretely rising hold off times; and

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With reference to FIG. 4, the plurality of resettable delay line segments 210 might comprise parallel segmented delay traces. A person hold off line segment could have only one hold off component that generates the minimum amount delayed monotone sign.

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eighteen. The equipment for detecting clock tampering as defined in declare fifteen, whereby the evaluate circuit decides whether or not the quantity of ones while in the plurality of delayed monotone alerts differs from the h2o level amount by in excess of a predetermined threshold to detect a clock fault.